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fedl610q111-01 issue date: sep. 26, 2013 ml610q111/ML610Q112 8-bit microcontroller 1/26 general description this lsi is a high-performance 8-bit cmos microcontroller into which rich peripheral circuits, such as timers, pwm, uart, i 2 c bus interface (master/slave), synchronous serial port, voltage level supervisor analog comparators and 10-bit successive approximation type a/d converter, are incorporated around 8-bit cpu nx-u8/100. the cpu nx-u8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipe line architecture parallel processing. the flash rom that is installed as program memory, and the on-chip debug function that is installed, enable program debugging and programming on customer?s board. features z cpu ? 8-bit risc cpu (cpu name: nx-u8/100) ? instruction system: 16-bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? on-chip debug function ? minimum instruction execution time: ? 30.5us (@32.768khz system clock) ? 0.122us (@8.192mhz system clock) z internal memory ? ml610q111: flash memory : ? internal 24kbyte flash memory (12k x 16bit) for program including unusable 32byte test data area. ? internal 4kbyte flash memory (2k x 16bit) for data. sram : ? internal 2kbyte data ram (2k x 8bit) ? ML610Q112: flash memory : ? internal 32kbyte flash memory (16k x 16bit) for program including unusable 32byte test data area. ? internal 4kbyte flash memory (2k x 16bit) for data. sram : ? internal 4kbyte data ram (4k x 8bit) ? flash memory operating condition and specification ? refer to the chapter electrical characteristics ?flash memory specifiaction?. z interrupt controller ? 1 non-maskable interrupt source (internal source: 1(wdt)) ? 30 maskable interrupt sources (internal sources: 23, external source: 7) z time base counter (tbc) ? low-speed time base counter: 1 channel ? high-speed time base counter: 1 channel (this time base counter is divided by 1-16, then it can be used as a clock of the timer and pwm.)
fedl610q111-01 ml610q111/ML610Q112 2/26 z watchdog timer (wdt) ? non-maskable interrupt and reset (non-maskable interrupt is generated by the first overflow, and reset is generated by the second overflow) ? free running ? overflow period: 7 types selectable by software (23.4ms, 31.25ms, 62.5ms, 125ms, 500ms, 2s, and 8s) z timer ? 8-bit x 6 channels (16-bit configuration available, 16-bit x 3ch) ? supports auto reload timer mode/one shot timer mode ? timer count start/stop by software or external input trigger (timer function with external trigger input supports for only 2ch. selectable external pins/analog comparator output as an exeternal trigger.) ? the effective minimum pulse width of the external trigger input: timer clock 3 (about 183 ns @ 16.384 mhz) ? allows measurement of pulse width etc. using an external trigger input. ? 8-selectable clock frequency as counter clock per channel z pwm ? resolution 16-bit ? single output x 3ch, multiple three outputs x 1ch ? allows an output of the pwm signal in a cycle of about 122ns (@pllclk = 16.384mhz) to 2s (@lsclk = 32.768khz) ? supports one shot pwm mode ? pwm start/stop by software and external trigger input (selectable external pins, analog comparator ou tput or timer interrupt as external trigger) ? 3-selectable clock frequency as pwm clock per channel z uart ? txd/rxd x 2ch ? half-duplex communication ? bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? built-in baud rate generator z i 2 c bus interface ? master function: standard mode (100kbit/s@8mhz), fast mode (400kbit/s@8mhz) ? slave function : standard mode (100kbit/s) z synchronous serial port (ssio) ? 1ch ? master/slave selectable ? lsb first/msb first selectable ? 8-bit length/16-bit length selectable z successive approximation type a/d converter (sa-adc) ? 10-bit a/d converter ? analog input ? 6ch (ml610q111) ? 8ch (ML610Q112)
fedl610q111-01 ml610q111/ML610Q112 3/26 z analog comparator ? 2ch ? ch0: allows comparison of the voltage level of the two external pins or comparison of one external pin and internal reference voltage level. ? ch1: allows comparison of one external pin and internal reference voltage level ? input common mode voltage range : v dd = 0.1v to v dd - 1.5v ? internal reference voltage : 0.1-0.8v (selectable in 50mv increments) ? hysteresis (comparator0 only): 20mv(typ.) ? allows selection of with/without interrupt sampling and interrupt edge. z general-purpose ports (gpio) ? input/output port ? 15ch (ml610q111) ? 25ch (ML610Q112) z reset ? reset by the reset_n pin ? reset by power-on detection ? reset by the watchdog timer (wdt) 2nd overflow ? reset by the voltage level supervisor (vls) function: selectable by software z voltage level supervisor (vls) ? 2ch ? ch0: it can be used for voltage level detection reset ? ch1: it can be used for voltage level detection interrupt ? judgment accuracy: 3.0% (typ.) z clock ? low-speed clock: ? built-in rc oscillation (32.768khz) ? high-speed clock: ? built-in pll oscillation (16.384mhz) ? high-speed external clock (max. 8.192mhz) maximum cpu clock is 8.192mhz. ? selection of high-speed clock mode by software: ? built-in pll oscillation ? external clock z power management ? halt mode: instruction execution by cpu is suspended (peripheral circuits are in operating states) ? stop mode: stop of oscillation (operations of cpu and peripheral circuits are stopped.) ? clock gear: the frequency of system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock). ? block control function: power down (reset registers and stop clock supply) the circuits of unused peripherals.
fedl610q111-01 ml610q111/ML610Q112 4/26 z shipment ? ml610q111: 20-pin tssop: ml610q111-xxxtd (blank product: ml610q111-nnntd) ? ML610Q112: 32-pin lqfp: ML610Q112-xxxtc (blank product: ML610Q112-nnntc) z guaranteed operating range ? operating temperature (ambience): -40 c to 105 c (flash write/erase: -20 c to +85 c) ? operating voltage: vdd=2.7v to 5.5v
fedl610q111-01 ml610q111/ML610Q112 5/26 block diagram the block diagram is shown in figure 1. ? * ? means secondary function, tertiary function or quaternary function of each port. ?( ) *2 ? means the function of ML610Q112. figure 1. ml610q111/ML610Q112 block diagram program memory (flash) 24kbyte (32kbyte) *2 uart rxd0 txd0* int 2 ram 2kbyte (4kbyte) *2 interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 wdt int 6 8bit timer x 6 int 4 pwm gpio pa0 to pa2 (pc4 to pc7) *2 int 7 pb0 to pb7 data-bus pwmc* pwmd*, pwme* pwmf0* pwmf1* pwmf2* test reset_n power reset & test alu epsw1 - 3 psw elr1 - 3 lr ecsr1 - 3 dsr/csr pc greg 0 - 15 v dd v ss 10bit-adc ain0 to ain5(ain7) *2 int 1 vls int 2 i 2 c master/slave scl* sda* ssio sck* sout* sin* int 1 ( pd0 to pd5 ) *2 analog comparator x 2 cmp0p cmp0m int 2 cmp0out* cmp1out* cmp1p test reset_n clock generator int 1 data memory (flash) 4kbyte rxd1 txd1* pc0 to pc3
fedl610q111-01 ml610q111/ML610Q112 6/26 pin configuration (top view) z ml610q111-xxxtd the pin layout is shown in figure 2. * pin no.4-8, 12-15, 18, 19 can be used as external trigger of the timer e-f and pwmc-f. figure 2. ml610q111 tssop20 pin configuration cmp0out / clkin / pwme / exi2 / pa2 1 2 3 4 5 6 7 8 9 10 reset_n test txd1 / txd0 / pwmd / ain3 / exi5 / pb1 pwme / rxd1 / exi6 / pb2 txd1 / sin / exi7 / pb3 testf tmfout / pc3 cmp1out / outclk / pwmc / rxd0 / ain2 / exi4 / pb0 tm9out / pwmf0 / pc0 20 19 18 17 16 15 14 13 12 11 pc1 / pwmf1 pa0 / exi0 / ain0 / pwmc / outclk / tm9out pb7 / a in5 / rxd1 / lsclk / pwmf0 / pwmc v dd v ss pb6 / ain4 / clkin / sda / pwmf1 pb5 / cmp0m / rxd0 / sck / scl / pwmf2 pb4 / cmp0p / sout / txd0 / txd1 pa1 / exi1 / ain1 / cmp1p / pwmd / lsclk / tmfout pc2 / pwmf2
fedl610q111-01 ml610q111/ML610Q112 7/26 z ML610Q112-xxxtc the pin layout is shown in figure 3. * pin no.3, 5-8, 16-19, 24, 25 can be used as external trigger of the timer e- f and pwmc-f. figure 3. ML610Q112 lqfp32 pin configuration 26 pa0 / exi0 / ain0 / pwmc / outclk / tm9out 27 28 29 30 31 32 25 reset_n pc6 / ain6 pc1 / pwmf1 pc5 / sda pc4 / scl pd0 pc0 / pwmf0 / tm9out pd5 pwmf2 / pc2 pd4 pd3 tmfout / pc3 pd2 15 14 13 12 11 10 9 16 testf pb3 / exi7 / sin / txd1 pb2 / exi6 / rxd1 / pwme pb1 / exi5 / ain3 / pwmd / txd0 / txd1 n.c. pb0 / exi4 / ain2 / rxd0 / pwmc / outclk / cmp1out pd1 test 1 2 3 4 5 6 7 8 pa2 / exi2 / pwme / clkin / cmp0out pwmf1 / sda / clkin / ain4 / pb6 n.c. v ss v dd ain7 / pc7 24 23 22 21 20 19 18 17 txd1 / txd0 / sout / cmp0p / pb4 pwmf2 / scl / sck / rxd0 / cmp0m / pb5 pwmc / pwmf0 / lsclk / rxd1 / ain5 / pb7 cmp1p / ain1 / exi1 / pa1 / tmfout / lsclk / pwmd
fedl610q111-01 ml610q111/ML610Q112 8/26 pin list table 1. ml610q111/ML610Q112 pin list pin no. primary function secondary function tertiary function quaternary function 32 lqfp 20 tssop name i/o function name i/o function name i/o function name i/o function 21 16 v ss ? power supply ? ? ? ? ? ? ? ? ? 22 17 v dd ? power supply ? ? ? ? ? ? ? ? ? 9 9 testf ? test ? ? ? ? ? ? ? ? ? 32 2 rese t_n i system ? ? ? ? ? ? ? ? ? 1 3 test i/o test ? ? ? ? ? ? ? ? ? 25 19 pa0/ exi0/ ain0/ tntg * / pmtg ** i/o gpio/ exint/ sa-adc/ timer/ pwm pwmc o pwm outclk o system tm9out o timer 16 12 pa1/ exi1/ ain1/ cmp1p/ tntg * / pmtg ** i/o gpio/ exint/ sa-adc/ comp/ timer/ pwm pwmd o pwm lsclk o system tmfout o timer 8 8 pa2/ exi2/ tntg * / pmtg ** i/o gpio/ exint/ timer/ pwm pwme o pwm clkin i system cmp0out o comp 3 4 pb0/ exi4/ ain2/ rxd0/ tntg * / pmtg ** i/o gpio/ exint/ sa-adc/ uart/ timer/ pwm pwmc o pwm outclk o system cmp1out o comp 5 5 pb1/ exi5/ ain3/ tntg * / pmtg ** i/o gpio/ exint/ sa-adc/ timer/ pwm pwmd o pwm txd0 o uart txd1 o uart 6 6 pb2/ exi6/ rxd1/ tntg * / pmtg ** i/o gpio/ exint/ uart/ timer/ pwm pwme o pwm ? ? ? ? ? ? 7 7 pb3/ exi7/ tntg * / pmtg ** i/o gpio/ exint/ timer/ pwm sin i ssio txd1 o uart ? ? ? 17 13 pb4/ cmp0p i/o gpio/ comp sout o ssio txd0 o uart txd1 o uart 18 14 pb5/ rxd0/ cmp0m i/o gpio/ uart/ comp sck i/o ssio scl i/o i 2 c pwmf2 o pwm 19 15 pb6/ ain4 i/o gpio/ sa-adc clkin i system sda i/o i 2 c pwmf1 o pwm 24 18 pb7/ ain5/ rxd1 i/o gpio/ sa-adc/ uart lsclk o system pwmf0 o pwm pwmc o pwm 30 1 pc0 i/o gpio ? ? ? pwmf0 o pwm tm9out o timer 27 20 pc1 i/o gpio ? ? ? pwmf1 o pwm ? ? ? 14 11 pc2 i/o gpio ? ? ? pwmf2 o pwm ? ? ? 11 10 pc3 i/o gpio ? ? ? ? ? ? tmfout o timer
fedl610q111-01 ml610q111/ML610Q112 9/26 pin no. primary function secondary function tertiary function quaternary function 32 lqfp 20 tssop name i/o function name i/o function name i/o function name i/o function 29 ? pc4 i/o gpio scl i/o i 2 c ? ? ? ? ? ? 28 ? pc5 i/o gpio sda i/o i 2 c ? ? ? ? ? ? 26 ? pc6/ ain6 i/o gpio/ sa-adc ? ? ? ? ? ? ? ? ? 23 ? pc7/ ain7 i/o gpio/ sa-adc ? ? ? ? ? ? ? ? ? 31 ? pd0 i/o gpio/ ? ? ? ? ? ? ? ? ? 2 ? pd1 i/o gpio/ ? ? ? ? ? ? ? ? ? 10 ? pd2 i/o gpio ? ? ? ? ? ? ? ? ? 12 ? pd3 i/o gpio ? ? ? ? ? ? ? ? ? 13 ? pd4 i/o gpio ? ? ? ? ? ? ? ? ? 15 ? pd5 i/o gpio ? ? ? ? ? ? ? ? ? * : tntg = tetg, tftg. ** : pmtg = pctg, pdtg, petg, pftg.
fedl610q111-01 ml610q111/ML610Q112 10/26 pin description table 2. ml610q111/ML610Q112 pin description pin name i/o description primary secondary tertiary, quaternary logic system reset_n i reset input pin. when this pin is set to ?l? level, system reset mode is set and the internal section is initialized. when this pi n is set to ?h? level subsequently, program execution starts. a pull-up resistor is internally connected. primary negative clkin i high-speed clock input pin. this pin is used as the secondary function of pb6 pin and also as the tertiary function of pa2 pin. secondary, tertiary ? lsclk o low-speed clock output pin. this pin is used as the secondary function of pb7 pin and also as the tertiary function of the pa1. secondary, tertiary ? outclk o high-speed clock output pin. this pin is used as the tertiary function of the pa0 and pb0 pin. tertiary ? general purpose input/output port pa0 to pa2 pb0 to pb7 pc0 to pc7 pd0 to pd5 i/o general-purpose input/output port. since these pins have secondary, tertiary or quaternary functions, the pins cannot be used as a port when the secondary, tertiary or quaternary functions are used. primary positive synchronous serial i/o sin i synchronous serial data input pin. this pin is used as the secondary function of pb3 pin. secondary positive sck i/o synchronous serial clock input/output pin. this pin is used as the secondary function of pb5 pin. secondary ? sout o synchronous serial data output pin. this pin is used as the secondary function of pb4 pin. secondary positive uart txd0 o uart0 data output pin. this pin is used as the te rtiary function of the pb1 and pb4 pin. tertiary positive rxd0 i uart0 data input pin. this pin is used as th e primary function of the pb0 and pb5 pin primary positive txd1 o uart1 data output pin. this pin is used as the tertiary function of the pb3 pin and also the quaternary function of the pb1 and pb4 pin. tertiary quaternary positive rxd1 i uart1 data input pin. this pin is used as the primary function of the pb2 and pb7 pin. primary positive i 2 c bus interface scl i/o serial clock input/output. this pin is used as the tertiary function of the pb5 and the secondary function of the pc4 pin. tertiary secondary positive sda i/o serial data input/output. this pin is used as the tertiary function of the pb6 and the secondary function of the pc5 pin. tertiary secondary positive pwm pwmc o pwmc output pin. this pin is used as the secondary function of the pa0 and pb0 and also the quaternary function of the pb7 pin. secondary quaternary positive/ negative pwmd o pwmd output pin. this pin is used as the secondary function of the pa1 and pb1 pin. secondary positive/ negative pwme o pwme output pin. this pin is used as the secondary function of the pa2 and pb2 pin. secondary positive/ negative pwmf0 o pwmf0 output pin. this pin is used as the tertiary function of the pb7 and pc0 pin. tertiary positive/ negative pwmf1 o pwmf1 output pin. this pin is used as the tertiary function of the pc1 and also the quaternary function of pb6 pin. tertiary/ quaternary positive/ negative
fedl610q111-01 ml610q111/ML610Q112 11/26 pwmf2 o pwmf2 output pin. this pin is used as the tertiary function of the pc2 and also the quaternary function of the pb5 pin. tertiary/ quaternary positive/ negative pin name i/o description primary secondary tertiary, quaternary logic external interrupt exi0 to 2 i external maskable interrupt input pins. interrupt enable and edge selection can be p erformed for each bit by software. these pins are used as the primary functions of the pa0 ? pa2 pins. primary positive/ negative exi4 to 7 i external maskable interrupt input pins. interrupt enable and edge selection can be p erformed for each bit by software. these pins are used as the primary functions of the pb0 ? pb3 pins. primary positive/ negative timer tete, tftg i external clock input pin used for both timer e and timer f.these pins are used as the primary function of the pa0-pa2, pb0-pb7 pins. primary ? tm9out o timer 9 output pin. this pin is used as the quat ernary function of the pa0 and pc0 pin. quaternary positive tmfout o timer f output pin. this pin is used as the quat ernary function of the pa1 and pc3 pin. quaternary positive successive approximation type a/d converter ain0 i channel 0 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pa0 pin. primary ? ain1 i channel 1 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pa1 pin. primary ? ain2 i channel 2 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pb0 pin. primary ? ain3 i channel 3 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pb1 pin. primary ? ain4 i channel 4 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pb6 pin. primary ? ain5 i channel 5 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pb7 pin. primary ? ain6 i channel 6 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pc6 pin. primary ? ain7 i channel 7 analog input for successive approximation type a/d converter. this pin is used as the primary function of the pc7 pin. primary ? comparator cmp0p i non-inverting input for comparator0. this pin is used as the primary function of the pb4 pin. primary ? cmp0m i inverting input for comparator0. this pin is used as the primary function of the pb5 pin. primary ? cmp0out o output for comparator0. this pin is used as the quaternary function of the pa2 pin. quaternary ? cmp1p i non-inverting input for comparator1. this pin is used as the primary function of the pa1 pin. primary ? cmp1out o output for comparator1. this pin is used as the quaternary function of the pb0 pin. quaternary ? test test i/o input/output pin for testing. a pull-dow n resistor is internally connected. ? positive testf ? test pin for flash memory. a pull-down resistor is internally connected. ? ? power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin. ? ?
fedl610q111-01 ml610q111/ML610Q112 12/26 termination of unused pins table 3 shows methods of terminating the unused pins for ml610q111/ML610Q112 table 3. termination of unused pins pin recommended pin termination reset_n open test open testf open pa0 to pa2 open pb0 to pb7 open pc0 to pc7 open pd0 to pd5 open n.c. open note : it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.
fedl610q111-01 ml610q111/ML610Q112 13/26 electrical characteristics z absolute maximum ratings (v ss =0v) parameter symbol condition rating unit power supply voltage v dd ta = 25 c -0.3 to +7.0 v input voltage v in ta = 25 c -0.3 to v dd +0.3 v output voltage v out ta = 25 c -0.3 to v dd +0.3 v output current i out ta = 25 c -12 to +11 ma power dissipation pd ta = 25 c 0.84 w storage temperature t stg D -55 to 150 c z recommended operating conditions (v ss =0v) parameter symbol condition range unit operating temperature (ambience) t op D -40 to +105 c operating voltage v dd D 2.7 to 5.5 v z flash memory specification (v ss = 0v) parameter symbol condition rating unit at read -40 to +105 c operating temperature (ambience) t opf at write/erase -20 to +85 c c epd data flash memory (4kb) 6000 rewrite counts *1 c epp program flash memory 80 cycles D chip-erase program flash and data flash memory D D block-erase (program flash memory) 8 kb D block-erase (data flash memory) 4 kb erase unit D sector-erase (data flash memory) 1 kb erase time (max.) D chip-erase/block-erase/sector-erase 100 ms write unit D D 1word(2bytes) D write time (max.) D 1word(2bytes) 40 s data retention *2 y dr D 15 years * 1 : rewrite counts is counted as one even if you erase suspend. * 2 : however, keep active time of the lsi from exceeding ten years. in addition, following capability of flash memory is available; - security function: providing security id for the protection of program code implemented in flash memory - accidental-write protection: providing special sequence to protect accidental write data to flash memory. by writing ?0fax? a nd?0f5x? sequentially, before write/erase, writing one word is available just only one time. - erase interrupt function: in the case of external interrupt during erasing flash memory, erase execution is suspended. and th en the interrupt is activated. please re-erase after interrupt execution.
fedl610q111-01 ml610q111/ML610Q112 14/26 z dc characteristics (supply current) (v dd =2.7 to 5.5v, v ss =0v, t a =-40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit supply current 1 idd1 cpu : in stop state (all clock stop) v dd =5.0v D 1 50 a supply current 2 idd2 cpu : in halt state * 1 (only cr oscillation operates) v dd =5.0v D 240 D a supply current 3 idd3 cpu : cr32.768khz operating state * 2 (only cr oscillation operates) v dd =5.0v D 250 D a supply current 4 idd4 cpu : cr8.192mhz operating state* 3 (cr and pll osc illation operate) v dd =5.0v D 4 6 ma 1 * 1 : ltbc and wdt are operating ,and significant bits of blkcon0 to blkcon7 registers are all ?1?. * 2 : when the cpu operating rate is 100%. minimum instruction execution time: approx 30.52 s (at 32.768khz system clock) * 3 : when the cpu operating rate is 100%. minimum instruction execution time: approx 122 ns (at 8.192mhz system clock)
fedl610q111-01 ml610q111/ML610Q112 15/26 z dc characteristics (vls, comparator) (v dd =2.7 to 5.5v, v ss =0v, t a =-40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ta=25 c typ -3.0% typ +3.0% vls0 threshold voltage (v dd =fall) v vls0f D typ -5.0% 2.85 typ +5.0% ta=25 c typ -3.0% typ +3.0% vls0 threshold voltage (v dd =rise) v vls0r D typ -5.0% 2.92 typ +5.0% vls1=0 3.3 vls1=1 3.6 vls1=2 3.9 ta=25 c vls1=3 typ -3.0% 4.2 typ +3.0% vls1=0 3.3 vls1=1 3.6 vls1=2 3.9 vls1 threshold voltage (v dd =fall) v vls1 D vls1=3 typ -5.0% 4.2 typ +5.0% v comparator0 in-phase input voltage range v cmr D 0.1 D v dd -1.5 v ta=25 c , v dd = 5.0v 10 20 30 comparator0 hysteresis v hysp v dd = 5.0v 5 20 35 comparator0 input offset voltage v cmof ta=25 c , v dd = 5.0v D D 7 ta=25 c -25 D 25 comparator reference- voltage error * 1 v cmref D -50 D 50 mv 1 * 1 :comparator input offset voltage is included.
fedl610q111-01 ml610q111/ML610Q112 16/26 z dc characteristics (io pins) (v dd =2.7 to 5.5v, v ss =0v, t a =-40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit ioh=-3.0ma, v dd =4.5v* 1 ta= -40 to 85 c v dd -0.7 D D voh1 ioh=-3.0ma, v dd =4.5v* 1 v dd -0.8 D D iol=+8.5ma, v dd =4.5v* 1 ta= -40 to 85 c D D 0.6 output voltage1 ( test, pa0-2, pb0-7, pc0-7, pd0-5 ) vol1 iol=+8.5ma, v dd =4.5v* 1 D D 0.7 output voltage2 (pb5, pb6 pc4, pc5) vol2 iol=+3.0ma D D 0.4 v 2 iooh voh = v dd (in high-impedance state) D D 1 output leakage ( pa0-2, pb0-7, pc0-7, pd0-5 ) iool vol = v ss (in high-impedance state) -1 D D a 3 iih1 vih1 = v dd D D 1 input current 1 ( reset_n ) iil1 vil1 = v ss, v dd = 5.0v ? 650 ? 500 ? 350 iih2 vih2= v dd = 5.0v 20 115 200 input current 2 ( test ) iil2 vil2 = v ss ? 1 D D iih3 vih3 = v dd = 5.0v (when pulled-down) 20 115 200 iil3 vil3 = v ss, v dd = 5.0v (when pulled-up) ? 200 ? 100 ? 20 iih3z vih3 = v dd (in high-impedance stat) D D 1 input current 3 ( pa0-2, pb0-7, pc0-7, pd0-5 ) iil3z vih3 = v ss (in high-impedance stat) -1 D D a 4 * 1 : when the one terminal output state. (v dd =2.7 to 5.5v, v ss =0v, t a =-40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measuring circuit vih1 D 0.7 v dd D v dd v input voltage 1 ( reset_n, test, pa0-2, pb0-7, pc0-7, pd0-5 ) vil1 D 0 D 0.3 v dd 2 input pin capacitance ( pa0-2, pb0-7, pc0-7, pd0-5 ) cin f = 10khz ta = 25 c D D 20 pf D
fedl610q111-01 ml610q111/ML610Q112 17/26 z measuring circuits measuring circuit 1 v v dd v ss vih vil *1: input logic circuit to determine the specified measuring conditions. *2: measured at the specified output pins. *3: measured at the specified input pins. (*2) (*1) (*3) measuring circuit 4 measuring circuit 2 v dd v ss vih vil (*2) a v dd v ss a input pins v dd v ss a c v : 1 f output pins output pins input pins input pins input pins output pins output pins measuring circuit 3 c v
fedl610q111-01 ml610q111/ML610Q112 18/26 z ac characteristics (clock) (v dd =2.7 to 5.5v, v ss =0v, t a =-40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit ta = -20 to 85 c typ. -3% typ. +3% 32khz rc oscillation frequency f rcl D typ. -4% 32.768 typ. +4% khz ta = -20 to 85 c typ. -3% typ. +3% pll oscillation frequency *1 f pll D typ. -4% 16.384 typ. +4% mhz * 1 : 1024 clock average. maximum cpu clock frequency is f pll /2. z ac characteristics (power on / reset sequence) (v dd =2.7 to 5.5v, v ss =0v, t a =-40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit reset pulse width p rst D 100 D D s reset noise elimination pulse width p nrst D D D 0.4 power-on reset activation power rise time t por D D D 10 ms p rst reset_n vdd 0.9*v dd 0.3*v dd vdd 0.9*v dd 0.1*v dd t por p rst 0.3*v dd 0.3*v dd powe r -on reset sequence external reset sequence
fedl610q111-01 ml610q111/ML610Q112 19/26 z ac characteristics (external interrupt) (v dd =2.7 to 5.5v, v ss =0v, t a =-40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation 2.5 x sysclk D 3.5 x sysclk t nul pa0 - pa2, pb0 - pb3 pa0 - pa2, pb0 - pb3 pa0 - pa2, pb0 - pb3 t nul (rising-edge interrupt) (falling-edge interrupt) (both-edge interrupt) t nul
fedl610q111-01 ml610q111/ML610Q112 20/26 z ac characteristics (synchronous serial port) (v dd =2.7 to 5.5v, v ss =0v, t a =-40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit when high-speed oscillation is not active 10 D D s sck input cycle (slave mode) t scyc when high-speed oscillation is active 500 D D ns sckoutput cycle (master mode) t scyc D D sck* 1 D s when high-speed oscillation is not active 4 D D s sck input pulse width (slave mode) t sw when high-speed oscillation is active 200 D D ns sck output pulse width (master mode) t sw D t scyc 0.4 t scyc 0.5 t scyc 0.6 s sout output delay (slave mode) t sd D D D 180 ns sout output delay (master mode) t sd D D D 80 ns sin input setup time (slave mode) t ss D 50 D D ns sin input hold time t sh D 50 D D ns * 1 : clock period selected with s0ck3-0 of the serial port 0 mode register(sio0mod1) t sd sck0 sin0 sout0 t sd t ss t sh t sw t scyc t sw
fedl610q111-01 ml610q111/ML610Q112 21/26 z ac characteristics (i 2 c bus interface: standard mode 100khz) (v dd =2.7 to 5.5v, v ss =0v, t a =-40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl D 0 D 100 khz scl hold time (start/restart condition) t hd:sta D 4.0 D D s scl?l? level time t low D 4.7 D D s scl?h? level time t high D 4.0 D D s scl setup time (restart condition) t su:sta D 4.7 D D s sda hold time t hd:dat D 0 D D s sda setup time t su:dat D 0.25 D D s sda setup time (stop condition) t su:sto D 4.0 D D s bus-free time t buf D 4.7 D D s z ac characteristics (i 2 c bus interface: fast mode 400khz) (v dd =2.7 to 5.5v, v ss =0v, tj=-40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl D 0 D 400 khz scl hold time (start/restart condition) t hd:sta D 0.6 D D s scl?l? level time t low D 1.3 D D s scl?h? level time t high D 0.6 D D s scl setup time (restart condition) t su:sta D 0.6 D D s sda hold time t hd:dat D 0 D D s sda setup time t su:dat D 0.1 D D s sda setup time (stop condition) t su:sto D 0.6 D D s bus-free time t buf D 1.3 D D s scl sda start condition restart condition stop condition t buf t hd:sta t low t high t su:sta t hd:sta t su:dat t hd:dat t su:sto
fedl610q111-01 ml610q111/ML610Q112 22/26 z electrical characteristics of successive approximation type a/d converter (v dd =2.7 to 5.5v, v ss =0v, t a =-40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit resolution n D D D 10 bit integral non-linearity error inl D -4 D +4 differential non-linearity error dnl D -3 D +3 zero-scale error v off D -4 D +4 full-scale error fse D -4 D +4 lsb conversion time t conv D D 102 D /ch : period of osclk (more than 3mhz) a v dd v ss analog input - ri 5k a in 0.1 f + 10 f
fedl610q111-01 ml610q111/ML610Q112 23/26 package dimensions z ml610q111-xxxtd figure 4 tssop20
fedl610q111-01 ml610q111/ML610Q112 24/26 z ML610Q112-xxxtc figure 5 lqfp32 z notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl610q111-01 ml610q111/ML610Q112 25/26 revision history page document no. date previous edition current edition description fedl610q111-01 2013.9.26 D D final edition 1
fedl610q111-01 ml610q111/ML610Q112 26/26 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants and any othe r information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accord ance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerosp ace machinery, nuclear-reactor controller, fuel-controller or ot her safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above specia l purposes. if a product is intended to be used for any such speci al purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013 lapis semiconductor co., ltd.

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